------------------------------------------------//库声明
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
USE IEEE.STD_LOGIC_ARITH.ALL;

------------------------------------------------//实体定义
ENTITY addr_count IS
PORT
(   clk_in : IN STD_LOGIC;
      addr : OUT std_logic_vector(5 downto 0)
		   );
END addr_count;

------------------------------------------------//结构体定义
ARCHITECTURE behave OF addr_count IS

------------------------------------------------//信号量定义
SIGNAL addr_temp: std_logic_vector(5 downto 0);

BEGIN 

------------------------------------------------//进程1，地址产生
    PROCESS(clk_in)
    BEGIN  
        IF (clk_in'EVENT AND clk_in ='1') THEN
            IF (addr_temp= "111111") THEN
                addr_temp <= "000000";
            ELSE addr_temp <= addr_temp+'1';
            END IF;
        END IF;
    END PROCESS;
	
------------------------------------------------//赋值	
	 addr <= addr_temp;
	 
END behave;